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Lookup NU author(s): Dr Kelvin Kwa, Dr Sanatan Chattopadhyay, Dr Sarah Olsen, Luke Driscoll, Professor Anthony O'Neill
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It is demonstrated from experimental I-V and C-V data, and confirmed by computer simulation, that strained Si/SiGe MOSFET performance severely degrades below a channel thickness of 7 nm. MOSFETs with strained Si channels of thickness 5 nm, 7 nm and 9 nm have been fabricated using a conventional high thermal budget process. The performance degradation is attributed to Ge diffusion through the strained Si layer, which causes a build up of gate oxide charge. (9 References).
Author(s): Kwa KSK, Chattopadhyay S, Olsen SH, Driscoll LS, O'Neill AG
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: 33rd European Solid-State Device Research
Year of Conference: 2003
Pages: 501-504
Publisher: IEEE
URL: http://dx.doi.org/10.1109/ESSDERC.2003.1256923
DOI: 10.1109/ESSDERC.2003.1256923
Notes: Franca J Freitas P Piscataway, NJ, USA. ESSDERC 2003. Proceedings of the 33rd European Solid-State Device Research - ESSDERC '03. Estoril, Portugal. IEEE. EDS. Infineon Technol. ATMEL. Tower Semiconductor Ltd. 16-18 Sept. 2003.
Library holdings: Search Newcastle University Library for this item
ISBN: 0780379993
