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Lookup NU author(s): Dr Sanatan Chattopadhyay, Professor Alex Yakovlev
In this article, we explore the impact of strain on circuit performance when strained silicon (s-Si) devices are used for designing low-power high-speed circuits. Emphasis has been given on the evaluation of noise characteristics and low-power performance along with the delay characteristics under different channel straining conditions. An inverter circuit has been used for performance evaluation through simulation where the device simulator is calibrated with experimental device data. The result shows a great promise for s-Si technology in digital applications which require high throughput and low power. © 2007 IEEE.
Author(s): Ramakrishnan H, Maharatna K, Chattopadhyay S, Yakovlev A
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: IEEE International Symposium on Circuits and Systems
Year of Conference: 2007
Pages: 1153-1156
Date deposited: 26/05/2010
Publisher: Institute of Electrical and Electronics Engineers
URL: http://dx.doi.org/10.1109/ISCAS.2007.378254
DOI: 10.1109/ISCAS.2007.378254
