Browse by author
Lookup NU author(s): Dr Nikolai Starodoubtsev, Dr Alex Bystrov, Professor Alex Yakovlev
Full text for this publication is not currently held within this repository. Alternative links are provided below where available.
A structural discipline for constructing speed-independent (hazard-free) circuits based on canonical chains of set-dominant and reset-dominant latches is proposed. The method can be applied to decompose complex asymmetric C-gate generated by logic synthesis from Signal Transition Graphs, and to map them into a restricted gate array ASIC library, such as IBM SA-12E that consists of logic gates with maximum four inputs and includes AO12, AOI12, OA12 and OAI12. The method is illustrated by new implementations of practically useful asynchronous circuits: a toggle element and an edge-triggered latch controller.
Author(s): Starodoubtsev N, Bystrov A, Yakovlev A
Publication type: Article
Publication status: Published
Journal: Lecture Notes in Computer Science: Integrated Circuit Design
Year: 2000
Volume: 1918
Pages: 168-177
Print publication date: 01/01/2000
ISSN (print): 0302-9743
ISSN (electronic): 1611-3349
Publisher: Springer
URL: http://dx.doi.org/10.1007/3-540-45373-3_17
DOI: 10.1007/3-540-45373-3_17
Altmetrics provided by Altmetric