Browse by author
Lookup NU author(s): Professor David Kinniment
Full text for this publication is not currently held within this repository. Alternative links are provided below where available.
There is considerable interest at present in the design of asynchronous systems based on the use of self-timing components for arithmetic and other operations. Amongst the advantages claimed for asynchronous design are ease of design, high speed, low power, and device speed independence. An often quoted example of the speed improvement possible from self-timed hardware is parallel binary addition, where the carry signals in the worst case must propagate through n stages before the sum can be guaranteed correct. In practice, however, it is not possible to achieve significant speed advantage from the method, and this paper shows that asynchronous adders only give a performance improvement over more conventional hardware in very limited conditions, where the size and regularity of the layout are at a premium. © 1996 IEEE.
Author(s): Kinniment DJ
Publication type: Review
Publication status: Published
Journal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year: 1996
Volume: 4
Issue: 1
Pages: 137-140
Print publication date: 01/01/1996
ISSN (print): 1063-8210
ISSN (electronic): 1557-9999
URL: http://dx.doi.org/10.1109/92.486088
DOI: 10.1109/92.486088