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Lookup NU author(s): Esmail Ashmila, Emeritus Professor Satnam Dlay, Emeritus Professor Oliver Hinton
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This paper presents a novel methodology to significantly improve the speed performance of a 32 bit estimated carry (ESTC) adder and extends the theory of the ESTC adder, and shows that further performance benefits can be achieved by using the statistical approach together with multiple carries. The simulation results for multiple carries, shows that the 32-bit adder can achieve dramatic speed advantages over other adders. Furthermore, the comparison in term of delay-area product shows a saving of 44.2% over a ripple adder, 41% over carry select adder; with ripple adder elements, and over 26% on carry select look-ahead adders. (12 References).
Author(s): Ashmila EM, Dlay SS, Hinton OR
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: Communication Systems, Networks and Digital Signal Processing (CSNDSP)
Year of Conference: 2004
Pages: 617-620
Notes: Dlay SS Newcastle upon Tyne, UK. Communication Systems, Networks and Digital Signal Processing. CSNDSP 2004. Fourth International Symposium. Newcastle upon Tyne, UK. 20-22 July 2004.
