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Approximate digital-in analog-out multiplier with asymmetric nonvolatility and low energy consumption

Lookup NU author(s): Shengqi YuORCiD, Professor Rishad Shafik, Dr Domenico Balsamo, Professor Alex Yakovlev

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Abstract

© 2023 The Author(s)Many modern compute-intensive applications require arithmetic results (usually multiplication) to be represented as analog signals. Using digital multipliers followed by digital-to-analog conversion (DAC) results in high energy and performance costs. This is because digital multipliers have costly carry propagation, and DAC circuits add associated conversion costs. Another concern, especially for arithmetic on the edge, is the need for nonvolatile operands in the face of power uncertainty. To deal with this, nonvolatile memory technologies have been combined with in-memory computing. This paper proposes a mixed-signal multiplier which directly generates an analog product based on two digital input operands. Fundamental to the design are transistor-memristor cells, organized in a crossbar structure. Using analog resistive partial product accumulation in the crossbar, the approximate multiplier eliminates the need for carry propagation and an explicit DAC. It also provides asymmetric nonvolatility making memristor writing a rare event, extending the application significance of the method. The design is shown to be functionally correct up to 4-bit, and achieves 8× to over 300× speedup, competitive peak-power and orders of magnitude energy reduction, compared with existing full-digital memristor-based multipliers and low-power multiplication DAC solutions.


Publication metadata

Author(s): Yu S, Xia F, Shafik R, Balsamo D, Yakovlev A

Publication type: Article

Publication status: Published

Journal: Integration

Year: 2023

Volume: 93

Print publication date: 01/11/2023

Online publication date: 06/06/2023

Acceptance date: 30/05/2023

Date deposited: 10/07/2023

ISSN (print): 0167-9260

ISSN (electronic): 1872-7522

Publisher: Elsevier B.V.

URL: https://doi.org/10.1016/j.vlsi.2023.05.009

DOI: 10.1016/j.vlsi.2023.05.009


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