Derivation of the reliability metric for digital circuits

Abufalgha, MA; Bystrov, A

doi:10.1109/ETS.2017.7968224

Derivation of the reliability metric for digital circuits

Lookup NU author(s): Mohamed Abufalgha, Dr Alex Bystrov

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Abstract

© 2017 IEEE. With technology scaling, the vulnerability of combinational circuits is increased, so evaluating their reliability becomes an essential demand. In this paper a simple yet effective method is proposed to derive the reliability of a combinational circuit. The idea of this method is to prevent the complexity of the traditional methods that use multi-iteration statistical procedures. This goal is achieved by dividing the problem into two parts, one describing the cause of the error, and the other part is involved on the circuit under test. The cause of the error is represented as a stochastic model of the interference, which can be considered as a fixed model for a specific design. The other part is derived by applying the stochastic fault model on the circuit under test using a simulation tool. A critical values are obtained by the second part, these values are the boundaries between two regions; error region and error-free region. The next step is to find the probability of error-free region by using some mathematical procedures. The probability of the error-free region can be interpreted as a reliable operating mode of that circuit. For the sake of simplicity, the proposed method is applied to a chain of inverters. A trade-off relation between energy, performance and reliability is obtained. A slow stage is added to the circuit under test to see its effect on the reliability of the circuit.