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Lookup NU author(s): Professor Alex Yakovlev, Dr Terrence Mak
This work is licensed under a Creative Commons Attribution 4.0 International License (CC BY 4.0).
© 2017 by the authors. Licensee MDPI, Basel, Switzerland. To meet the performance and scalability demands of the fast-paced technological growth towards exascale and big data processing with the performance bottleneck of conventional metal-based interconnects (wireline), alternative interconnect fabrics, such as inhomogeneous three-dimensional integrated network-on-chip (3D NoC) and hybrid wired-wireless network-on-chip (WiNoC), have emanated as a cost-effective solution for emerging system-on-chip (SoC) design. However, these interconnects trade off optimized performance for cost by restricting the number of area and power hungry 3D routers and wireless nodes. Moreover, the non-uniform distributed traffic in a chip multiprocessor (CMP) demands an on-chip communication infrastructure that can avoid congestion under high traffic conditions while possessing minimal pipeline delay at low-load conditions. To this end, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in such emerging hybrid NoCs. The proposed router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low-loads. When the output port required for intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a non-speculative low-latency pipeline. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in hybrid NoCs to achieve low-latency communication under various traffic loads. Simulation shows that the proposed router can reduce applications’ execution time by an average of 16.9% compared to low-latency routers, such as SWIFT. By reducing the latency between 2D routers (or wired nodes) and 3D routers (or wireless nodes), the proposed router can improve the performance efficiency in terms of average packet delay by an average of 45% (or 50%) in 3D NoCs (orWiNoCs).
Author(s): Agyeman MO, Zong W, Yakovlev A, Tong K-F, Mak T
Publication type: Article
Publication status: Published
Journal: Journal of Low Power Electronics and Applications
Year: 2017
Volume: 7
Issue: 2
Online publication date: 26/04/2017
Acceptance date: 20/04/2017
Date deposited: 10/07/2017
ISSN (electronic): 2079-9268
Publisher: MDPI AG
URL: https://doi.org/10.3390/jlpea7020008
DOI: 10.3390/jlpea7020008
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