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Efficient encoding of instructions of ARM Cortex M0+ processor

Lookup NU author(s): Alessandro De Gennaro, Paulius Stankaitis

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Abstract

As the complexity of digital hardware grows steadily, so does the demand of high level modelling systems to abstract the low level implementation of synchronous and asynchronous digital circuits. Conditional partial order graphs representation provides a compact and solid approach to represent event-based systems, and together with Workcraft design tool, they represent an extremely efficient development environment to create any system. So far, the synthesis phase of the controller for managing the whole datapath structure lacked an efficient encoding association mechanism, as well as a friendly and customisable user interface to encode the Partial order graphs. The following paper aims at bridging this gap, providing a graphical user interface integrated in Workcraft, new algorithms for the generation of encodings for the Partial orders composing the system and the possibility to customise the final op-codes, if needed. All these features have been tested on the Instruction Set Architecture ARMv6-M, integrated into the ARM Cortex M0+ microprocessor showing quite a big improvement in terms of area of the final controller with respect to previous approaches.


Publication metadata

Author(s): de Gennaro A, Stankaitis P

Publication type: Report

Publication status: Published

Series Title: School of Computing Science Technical Report Series

Year: 2015

Pages: 11

Online publication date: 01/01/2015

Report Number: 1442

Institution: School of Computing Science, University of Newcastle upon Tyne

Place Published: Newcastle upon Tyne

URL: http://www.cs.ncl.ac.uk/publications/trs/papers/1442.pdf


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