Complementary JFET Logic for Low-Power Applications in Extreme Environments

Habib, H; Wright, NG; Horsfall, AB

doi:10.4028/www.scientific.net/MSF.740-742.1052

Complementary JFET Logic for Low-Power Applications in Extreme Environments

Lookup NU author(s): Hassan Habib, Professor Nick Wright, Dr Alton Horsfall

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Abstract

The static and dynamic characteristics of complementary JFET (CJFET) logic inverter are studied across a range of temperatures and supply voltages to assess potential improvements in performance of digital logic functions for operation in extreme environments. The logic inverter is truly the core of all digital designs. The design and analysis of an inverter enables the design of more complex structures, such as NAND, NOR and XOR gates. These complex structures in turn form the building blocks for modules, such as adders, multipliers and microprocessors. At 500 degrees C and operating at a supply voltage of 1 V, the CJFET inverter have noise margin comparable to that of room temperature silicon and strained silicon CMOS inverters. Furthermore, the static power dissipation by CJFET inverter is 20.6 nW which is six orders of magnitude lower than that by current SiC technologies, making CJFET technology ideal for achieving complex logic functions, far greater than a few-transistors ICs, in the nearer term.