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Lookup NU author(s): Dr Stephen McGough, Emeritus Professor Isi Mitrani
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Algorithms for simulating an ATM switch on a number of parallel processors are described. These include parallel generation and merging of bursty arrival sources, marking and deleting of lost cells due to buffer overflows, and, in one version of the algorithm, computation of departure instants. When the number of lost cells is relatively small, the run time of the simulation is approximately O(N/P), where N is the total number of cells simulated and P the number of processors. The cells are processed in batches of fixed size; that size affects both the structure and the performance of the algorithms.
Author(s): McGough AS, Mitrani I
Publication type: Article
Publication status: Published
Journal: Performance Evaluation (Special Issue on ATM Networks: Performance Modelling and Analysis)
Year: 2000
Volume: 41
Issue: 2-3
Pages: 149-164
ISSN (print): 0166-5316
ISSN (electronic): 1872-745X
Publisher: Elsevier Science BV
URL: http://dx.doi.org/10.1016/S0166-5316(00)00007-9
DOI: 10.1016/S0166-5316(00)00007-9
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