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Mohammed Benaissa, Said BoussaktaFast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero

Lookup NU author(s): Professor Said Boussakta

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Abstract

Novel modulo 2n-1 addition algorithms for residue number system (RNS) applications are presented. The proposed algorithms depart from the traditional approach of modulo 2n-1 addition by setting the input carry in the first stage of the addition to one, which only ever produces one representation of zero. The resulting architectures not only offer significant speedup in a modulo 2n-1 addition, but they can also offer a reduction in area and thus provide improvements in the cost functions area times delay2 and energy times delay. The superiority of these architectures is validated through back-annotated VLSI designs using 130 nm CMOS technology.

Publication metadata

Author(s): Patel RA, Boussakta S

Publication type: Article

Publication status: Published

Journal: IEEE Transactions on Computers

Year: 2007

Volume: 56

Issue: 11

Pages: 1484-1492

Print publication date: 01/01/2007

Date deposited: 23/06/2010

ISSN (print): 0018-9340

ISSN (electronic): 1557-9956

Publisher: IEEE

URL: http://dx.doi.org/10.1109/TC.2007.70750

DOI: 10.1109/TC.2007.70750

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