Strained Si/SiGe MOS technology: Improving gate dielectric integrity

Olsen, SH; Yana, L; Agaiby, R; Escobedo-Cousin, E; O'Neill, AG; Hellstrom, PE; Ostling, M; Lyutovich, K; Kasper, E; Claeys, C; Parker, EHC

doi:10.1016/j.mee.2008.08.001

Strained Si/SiGe MOS technology: Improving gate dielectric integrity

Lookup NU author(s): Dr Sarah Olsen, Dr Enrique Escobedo-Cousin, Professor Anthony O'Neill

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Abstract

Strained Si is recognised as a necessary technology booster for the nanoelectronics regime. This work shows that high levels of stress attainable from globally strained Si/SiGe platforms can benefit gate leakage and reliability in addition to MOSFET channel mobility. Device self-heating due to the low thermal conductivity of SiGe is shown to be the dominating factor behind compromised performance against short channel strained Si/SiGe MOSFETs. Novel thin virtual substrates aimed at reducing self-heating effects are investigated. In addition to reducing self-heating effects, the thin Virtual substrates provide further improvements to gate oxide integrity, reliability and lifetime compared with conventional thick virtual substrates. This is attributed to tire lower surface roughness of the thin virtual substrates which arises due to the reduced interactions of strain-relieving misfit dislocations during thin Virtual substrate growth. Good agreement between experimental data and physical models is demonstrated, enabling gate leakage mechanisms to be identified. The advantages and challenges of using globally strained Si/SiGe to advance MOS technology are discussed. (C) 2008 Elsevier B.V. All rights reserved.